(a) Field of the Invention
The present invention relates to a liquid crystal display and, more particularly a thin film transistor array substrate with a low dielectric insulating layer, and a method of fabricating the same.
(b) Description of the Related Art
Generally, a thin film transistor array substrate is used as a circuit substrate for independently driving the respective pixels in a liquid crystal display or an organic electroluminescence display. The thin film transistor array substrate has generally gate lines for carrying scanning signals, data lines for carrying picture signals, thin film transistors connected to the gate and the data lines, pixel electrodes connected to the thin film transistors, a gate insulating layer covering the gate lines, and a passivation layer covering the thin film transistors and the data lines. Each thin film transistor is formed with a gate electrode connected to the gate line, a channel-forming semiconductor layer, a source electrode connected to the data line, a drain electrode, a gate insulating layer, and a passivation layer. The thin film transistor functions as a switching circuit where the picture signal from the data line is transmitted to the pixel electrode in accordance with the scanning signal from the gate line.
Liquid crystal displays are now widely used by consumers and the larger the size and the higher the definition of the display, the more popular. However, signal deformation becomes a problem with the larger size and capacity of the displays due to increased parasitic capacitance. Furthermore, as demand for liquid crystal displays for notebook computers having reduced power consumption and increased demand for liquid crystal display TVs with increased brightness, the opening ratio of the liquid crystal displays need to be increased.
To increase the opening ratio, the pixel electrodes over the data line assembly have to be extended to overlap with the data line assembly. In such case, the parasitic capacitance between the pixel electrodes and the data lines is increased. To avoid increases in parasitic capacitance, there should be sufficient vertical spacing between the pixel electrodes and the data lines. To provide such spacing, a passivation layer is usually formed with an organic insulating film. However, there are problems associated with the formation of the passivation layer using the organic insulating film. First, the material cost is high because there is a large amount of material loss from the spin coating process. Second, the organic insulating film has limited thermostability. Third, the formation of layer using an organic insulating film involves high frequency of occurrence of impure particles. Fourth, the organic insulating film is weaker in adhesive strength with respect to the neighboring layers. Fifth, when pixel electrodes are formed on the passivation layer, there is a high chance of etching error. Accordingly, a need exists for a method and a thin film transistor array substrate having a high opening ratio but without the above problems.